Using a JIT compiler to speed up execution of cycle accurate simulators

Art der Arbeit:
Studienarbeit/Diplomarbeit/Bachelor-Arbeit/Master-Arbeit
Betreuer:
Adresse: Sebastian Rachuj
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Martensstr. 3
91058 Erlangen
Germany
Raum: 07.135
Telefon: +49 9131 85 27612
Fax: +49 9131 85 27912
Homepage: http://www3.informatik.uni-erlangen.de/Persons/rachuj
E-Mail: sebastian.rachuj@fau.de
Beschreibung der Arbeit:

Detailed simulation of processors is really slow. To speed it up, a combination of cycle-accurate simulation and Just-In-Time compilation (JIT) can be used. The aim of this thesis is to use a JIT framework (like the unicorn engine) and combine it with a cycle-accurate model (e.g. RISC-V model using the verilator or gem5).

Bearbeitungszustand:
Offen