Wolfgang Bauer

Wolfgang Bauer

Since February 2017, Wolfgang Bauer is a member of the research staff at the Chair of Computer Architecture. He holds a Master's Degree (M.Eng.) in Electrical and Mechatronic Systems.


Address: Wolfgang Bauer
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Martensstraße 3
91058 Erlangen
Office: 07.125
Phone: +49 9131 85 27574
Fax: +49 9131 85 27912
Homepage: http://www3.informatik.uni-erlangen.de/Persons/bauerwo/
E-Mail: wolfgangm.bauer@fau.de

Research Interests

  • Hardware-near Simulation
  • Constraint Random Verification


  • Rachuj, Sebastian; Bauer, Wolfgang; Fey, Dietmar:
    Evaluation of a Sensor Fusion Algorithm on a Real-Time Processor.
    In: Wahl, Michael; VDE (Ed.): AmE 2018 - Automotive meets Electronics
    (AmE 2018 - Automotive meets Electronics, Dortmund, 07.03.-08.03.2018).
    2018, pp. 44-48.
  • Widerspick, Christian; Bauer, Wolfgang; Fey, Dietmar:
    Latency Measurements for an Emulation Platform on Autonomous Driving Platform NVIDIA Drive PX2.
    In: Trinitis, Carsten; Pionteck, Thilo (Ed.): ARCS Workshop 2018; 31th International Conference on Architecture of Computing Systems
    (3rd FORMUS³IC Workshop, Braunschweig, Germany,, 9 April 2018).
    Braunschweig, Germany: VDE-Verlag, 2018, pp. 117-126. - ISBN 978-3-8007-4559-3
  • Bauer, Wolfgang; Holzinger, Philipp; Reichenbach, Marc; Vaas, Steffen; Hartke, Paul; Fey, Dietmar:
    Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems.
    In: Repara 2018 (Org.): Euro-Par 2018: Parallel Processing Workshops
    (The 4th International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (Repara), Turin, Turin, Italien).
    Turin, Itatlien: Springer, 2018, pp. -.
  • Kohl, Johannes; Bauer, Wolfgang; Bäsig, Jürgen; Fey, Dietmar:
    Evaluating a Simulation based PLC Processor Optimization.
    In: eurosis (Ed.): ISC 2017
    (15th Annual Industrial Simulation Conference, Warsaw, Poland, 31.05.2017). vol. 15
    2017, pp. 61-66.
  • Kohl, Johannes; Bauer, Wolfgang; Bäsig, Jürgen; Rübesam, Stefan; Fey, Dietmar:
    Processor Error Detection Capabilities of Random Programs.
    In: GI / GMM / ITG (Org.): Tagungsband TuZ 2017
    (Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Lübeck, Germany, 06.03.2017). vol. 29
    2017, pp. 65-68.
  • Bauer, Wolfgang; Kohl, Johannes; Bäsig, Jürgen; Rübesam, Stefan; Fey, Dietmar:
    Generation of Executable Runtime Constrained Random Programs Functional Processor Verification.
    In: eurosis (Org.): ESM 2016
    (The European Simulation and Modelling Conferences, Gran Canaria, Spain, 26.10.2016). vol. 30
    2016, pp. 256-263.
  • Bauer, Wolfgang; Bäsig, Jürgen:
    Verification of specific processor pipeline stages with UVM.
    Talk: User2User, Mentor User Conference, Mentor Graphics
    München, 15.10.2015