Andreas Loos

From April 2009 to March 2010, Andreas Loos was a member of the research staff at the Chair of Computer Architecture.

He holds a Master's Degree (Diplom-Ingenieur (FH)).

Contact

Address: Dipl.-Ing. (FH) Andreas Loos
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Martensstr. 3
91058 Erlangen
Germany
Homepage: http://www3.informatik.uni-erlangen.de/Persons/loos/
E-Mail: andreas.loos@informatik.uni-erlangen.de

Publications

  • Schmidt, Michael; Reichenbach, Marc; Loos, Andreas; Fey, Dietmar:
    A Smart Camera Processing Pipeline for Image Applications Utilizing Marching Pixels.
    In: Signal & Image Processing : An International Journal (SIPIJ) Vol.2, No.3, September 2011 Vol. 2 (2011), no. 3, pp. 137-156
  • Loos, Andreas; Reichenbach, Marc; Fey, Dietmar:
    ASIC Architecture to Determine Object Centroids from Gray-Scale Images Using Marching Pixels.
    In: Al-Majeed, Salah S.; Hu, Chin-Lin; Nagamalai, Dhinaharan (Ed.): Advances in Wireless, Mobile Networks and Applications
    (International Conferences, WiMoA 2011 and ICCSEA 2011, Dubai, 25.-27.05.2011). vol. 154, 1. ed.
    Heidelberg: Springer, 2011, pp. 234-249. - ISBN 978-3-642-21152-2
  • Loos, Andreas; Schmidt, Michael; Fey, Dietmar; Gröbel, Jens:
    Dynamically programmable image processor for compact vision systems.
    In: IEEE Computer Society (Ed.): Proceedings of the 10th IEEE Conference on Computer and Information Technology
    (Computer and Information Technology (CIT), Bradford, UK, 29.06.2010-01.07.2010). vol. 1, 1. ed.
    IEEE, CS Digital Library: IEEE Computer Society, 2010, pp. 33-40. - ISBN 978-0-7695-4108-2
  • Loos, Andreas; Fey, Dietmar:
    A 2000 frames/s programmable binary image processor chip for real-time machine vision applications.
    In: n.b. (Ed.): Proc. Work-in-Progress Session 14th IEEE Real-Time and Embedded Technology and Application Symposium
    ((RTAS'08), St. Louis, MO, United States, April 2008).
    2008, pp. 49-52.
  • Fey, Dietmar; Gaede, Carsten; Loos, Andreas; Komann, Marcus:
    A new marching pixels algorithm for application-specific vision chips for fast detection of objects' centroids.
    In: n.b. (Ed.): Intern. Conf. on Parallel and Distributed Computing and Systems
    ((PDCS 2008), Orlando, Florida, USA, November 16 - 18, 2008).
    2008, pp. -.
  • Loos, Andreas; Schmidt, Michael; Fey, Dietmar; Gröbel, Jens:
    High speed binary image processor for compact real time vision systems.
    In: n.b. (Ed.): Proc. Conf. on Design and Architectures for Signal and Image Processing
    ((DASIP 2008), Bruxelles, Belgium, November 24 -26, 2008).
    2008, pp. 255-261.
  • Fey, Dietmar; Komann, Marcus; Schurz, Frank; Loos, Andreas:
    An organic computing architecture for visual microprocessors based on marching pixels.
    In: n.b. (Ed.): International Symposium on Circuits and Systems
    ((ISCAS 2007), New Orleans, Louisiana, USA, May 27-30, 2007).
    2007, pp. 2686-2689.
  • Schmidt, Michael; Loos, Andreas; Fey, Dietmar:
    A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems.
    In: n.b. (Ed.): Proc. of the 5th Intern. Symposium on Parallel Computing in Electrical Enineering
    ((PARELEC), Bialystok, Poland, September 2006).
    2006, pp. 374-379.
  • Loos, Andreas; Schmidt, Michael; Graupner, Achim; Fey, Dietmar; Schüffny, Rene:
    A combined space-time multiplex architecture for a stacked smart sensor chip.
    In: SPIE Digital Library (Ed.): Proc. SPIE, Vol. 6185 / Computer Architectures and Photonic Interconnects
    (Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration, Strasbourg, France, 3 April 2006).
    2006, pp. -.
  • Hoppe, Lutz; Förtsch, Michael; Loos, Andreas; Fey, Dietmar; Zimmermann, Horst:
    A parallel analogue-digital photodiode array processor chip with hard-wired morphologic algorithms.
    In: Chatard, Jean-Pierre; Dennis, Peter N. J. (Ed.): Proc. SPIE, Vol. 5964
    (Detectors and Associated Signal Processing II, Jena, Germany, 13 September 2005).
    2005, pp. 104-111.
  • Loos, Andreas; Fey, Dietmar; Graupner, Achim; Schüffny, Rene:
    Architektur und Realisierung parallelmorphologischer Algorithmen in einem CMOS-Bildsensor.
    In: n.b. (Ed.): Tagungsband 8. Workshop Optik in der Rechentechnik
    (8. Workshop Optik in der Rechentechnik, Ilmenau, Germany, 2005).
    2005, pp. 1-8.