Steffen Vaas, M.Sc.

Since April 2015, Steffen Vaas is a member of the research staff at the Chair of Computer Architecture.

Contact

Address: Steffen Vaas
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Martensstraße 3
91058 Erlangen
Germany
Office: 07.134
Phone: +49 9131 85 27028
Fax: +49 9131 85 27912
Homepage: http://www3.informatik.uni-erlangen.de/Persons/vaas
E-Mail: steffen.vaas@fau.de

Research Interests

  • Soft-Core Processors on FPGAs
  • Application-Specific Instruction-Set Processors (ASIP)
  • Deterministic Multi-Core Architectures for Safety-Critical Applications

Publications

  • Lieske, Tobias; Pfundt, Benjamin; Vaas, Steffen; Reichenbach, Marc; Fey, Dietmar:
    System on Chip Generation for Multi-Sensor and Sensor Fusion Applications.
    In: IEEE (Ed.): Proceedings of the 17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)
    (17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Island of Samos, Greece, 17-20 July, 2017).
    2017, pp. to be published.
  • Vaas, Steffen; Ulbrich, Peter; Reichenbach, Marc; Fey, Dietmar:
    The Best of Both: High-performance and Deterministic Real-Time Executive by Application-Specific Multi-Core SoCs.
    In: HEART (Org.): Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP '17)
    (Conference on Design and Architectures for Signal and Image Processing (DASIP '17), Dresden, 27.-29. September 2017).
    2017, pp. 0-0.
  • Vaas, Steffen; Reichenbach, Marc; Fey, Dietmar:
    An Application-Specific Instruction Set Processor for Power Quality Monitoring.
    In: O'Conner, Lisa (Ed.): Parallel and Distributed Processing Symposium Workshop (IPDPSW)
    (23th Reconfigurable Architectures Workshop (RAW), Chicago, May 23-24, 2016).
    -: IEEE International, 2016, pp. 181-188. - ISBN 978-1-5090-2140-6
  • Vaas, Steffen; Reichenbach, Marc; Stadelmayer, Thomas; Hofmann, Johannes; Fey, Dietmar:
    Embedded Parallel Computing Accelerators for Smart Control Units of Frequency Converters.
    In: Varbanescu, Ana Lucia (Ed.): ARCS 2016; 29th International Conference on Architecture of Computing Systems
    (12th Workshop on Parallel Systems and Algorithms (PASA), Nuremberg, 4-7 April 2016).
    Nuremberg, Germany: VDE VERLAG GMBH, Berlin, Offenbach, 2016, pp. 1-5. - ISBN 978-3-8007-4157-1
  • Vaas, Steffen; Reichenbach, Marc; Margull, Ulrich; Fey, Dietmar:
    The R2-D2 Toolchain – Automated Porting of Safety-Critical Applications to FPGAs.
    In: Cumplido, René (Org.): Proceedings of ReConFig' 16
    (2016 International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, 30.11.2016 - 02.12.2016).
    2016, pp. to be published.
  • Reichenbach, Marc; Lieske, Tobias; Vaas, Steffen; Häublein, Konrad; Fey, Dietmar:
    FAUPU - A Design Framework for the Development of Programmable Image Processing Architectures.
    In: Cumplido, René (Ed.): Proceedings of ReConFig' 15
    (2015 International Conference on ReConFigurable Computing and FPGAs, Mayan Riveria, Mexico, 07.-09.12.2015).
    2015, pp. 1-8.