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Chair of Computer Science 3
ParCA
Description
Theses
Contact
Dept. of Computer Science  > CS 3  > Research  > ParCA
ParCA

Description

In image-processing most tasks are very compute intensive. For example for image-pre-processing each middle point of multiple visible objects in a given image is to be found.
A very innovative possibility is the Marching Pixels approach: an emergent solution, based on the use of cellular automata computation.
Such cellular automata computation is a very compute intensive task, that can be efficiently parallelised. ParCA is therefore a system, that uses a single processor array, that works on a single partition of an input-image, representing a state of the basic cellular automata. So ParCA stands for partitioned cellular automata.
Systemoverview

System Characteristics
Camera: Global Memory: Processor Array:
  • delivers binary images directly in global memory
  • Controlled by the CPU
CPU:
  • Serves as Conroller for all other components
  • Loads the PE Program
  • DMA Controller for rapid Memoryaccess
  • Off-Chip
  • Holds all necessary Informations incl. programs for the CPU and PEs
Partitioning:
  • Only a small part of the whole CA fits into the chip
  • That is why we need to partition
  • Partitionorder is programmable
  • Works on a single partition, while the other is being loaded
  • Double-Buffering principle
  • Fully programmable in SIMD manner
  • Own instruction-set for neighborhood operations
  • Serial ALU

Current Results
FPGA Prototype
  • Partitions of 4x4 tested on a Xilinx Virtex2 FPGA
  • PowerPC HardIP core as CPU
  • Global Memory implemented as external DDR Ram
ASIC Implementation
  • Leon3 SoftIP core as CPU
  • Own DMA controller
  • Layout with 32x32 partition
  • SRAM macrocellblocks for partitions and program memory
Timings
  • At industrial resolution of 320x240 we achieve 91 FPS
  • In VGA resolution 23 FPS
  • 40 times faster than an embedded Intel Atom Processor

Bachelor and Master Theses

  • Marc Reichenbach, Ralf Seidler, Conception and Realization of a Fine-Granular Processor Field on FPGA Basis for Emergent Algorithms with Cellular Automata, Study Thesis, Friedrich-Schiller-University Jena, November 2009.
  • Marc Reichenbach,Umsetzung einer parallelen Architektur als ASIC,Master Thesis, Friedrich-Schiller-University, May 2010.
  • Benjamin Pfundt,Implementierung neuer Features in ParCA,Bachelor Thesis, Friedrich Alexander University Erlangen-Nuremberg, 2010.
There could be YOUR Bachelor or Master Thesis standing HERE!!
We are allways looking for interested students, participating in this hardware/software project! Possible areas of work include, but are not limited to: improvement of speeding up ParCA, improvement of ParCA for special algorithms.

Contact

Dipl.-Inf. Marc Reichenbach


  Contact Last modified: 2011-06-08 09:42:32   VS