Avinash Sodani, Chief Architect 'Knights Landing' Xeon-Phi processor at
Knights Landing Intel Xeon Phi CPU: Path to Parallelism with General Purpose
The demand for high performance will continue to skyrocket in the future fueled
by the drive to solve the challenging problems in science and to provide the
horsepower needed to support the compute-hungry use cases that are emerging in
consumer and commercial space. Exploiting parallelism will be crucial in
achieving the massive amounts of performance required to solve these problems.
This talk will present the new Xeon Phi Processor, called Knights landing, which
is architected to provide huge amounts of parallelism in a manner that is
accessible with general purpose programming. The talk will provide insight into
the important architecture features of the processor and explain their
implications on software. It will provide the inside story on the various
architecture decisions made on Knights Landing - why we architected the
processor the way we did. It will show measured performance numbers from the
Knights Landing silicon on range of workloads. The talk will conclude with sho
wing the historical trends in architecture and what they mean for software as we
extend the trends into the future.
Avinash Sodani is a Senior Principal Engineer at Intel Corporation and the chief
architect of the Xeon-Phi Processor called Knights Landing. He specializes in
the field of High Performance Computing (HPC). Previously, he was one of the
architects of the 1st generation Core processor, called Nehalem, which has
served as a foundation for today's line of Intel Core processors. Avinash is a
recognized expert in computer architecture and has been invited to deliver
several keynotes and public talks on topics related to HPC and future of
computing. Avinash holds over 20 US Patents and is known for seminal work on the
concept of "Dynamic Instruction Reuse". He has a PhD and MS in Computer Science
from University of Wisconsin-Madison and a B.Tech (Hon's) in Computer Science
from Indian Institute of Technology, Kharagpur in India.
Michael Wong, ISOCPP.org, OpenMP CEO
Massive Parallelism - C++ and OpenMP Parallel Programming Models of Today and Tomorrow
Why is the world rushing to add Parallelism to base languages when consortiums
and companies have been trying to fill that space for years? How is the
landscape of Parallelism changing in the various standards, and specifications?
I will give an overview as well as a deep dive into what C/C++ is doing to add
parallelism such as the proposaed Vector/SIMD model that employs implicit
Wavefront, but also how consortiums like OpenMP is pushing forward into the
world's first High-level Language support for GPGPU/Accelerators and SIMD
programming. Both are necessary to express the Massive Parallelism of tomorrow.
GPU/Accelerator computing looks to be here to stay. Whether it is a flash in the
pan or not, data parallelism is never going to be stale, especially for
high-performance computing. The good news is that Clang 3.7 has OpenMP 3.1
support through a collaborative effort between many institutions, and Clang 3.8
or later will have some form of of support for OpenMP 4 accelerators that
targets many different devices, including Intel Xeon Phi and NVIDIA GPUs. Other
compilers with high-level accelerator support will be GCC 6. The OpenMP model
was designed to fit all possible forms of accelerators. However, in a changing
world where discrete GPUs are transitioning into accelerated processing units
(APUs), and being combined with various forms of high-bandwidth memory (HBM), is
the OpenMP model, or even the OpenACC model, the best model? Should we begin
programming future devices with a new programming model that ignores the
"legacy" discrete systems and aims for the future? I'll contrast the OpenMP
design with the emerging C++ Standard design and how we can merge the design
experience from both HPC and consumer devices. As Char of C++ Standard's SG14:
Games Dev and Low Latency, I will show where we might be going in five years
with an accelerator model that is appropriate for the future with description of
Agency, SYCL, HCC, and HPX based on an outline of future goals.
Michael Wong is the CEO of OpenMP. He is the IBM and Canadian representative to
the C++ Standard and OpenMP Committee. He is also a Director of ISOCPP.org and a
VP, Vice-Chair of Programming Languages for Canada's Standard Council. He has so
many titles, it's a wonder he can get anything done.
He chairs the WG21 SG5 Transactional Memory and SG14 Games Development/Low
Latency, and is the co-author of a number C++11/OpenMP/Transactional Memory
features including generalized attributes, user-defined literals, inheriting
constructors, weakly ordered memory models, and explicit conversion operators.
Having been the past C++ team lead to IBM's XL C++ compiler means he has been
messing around with designing C++ compilers for twenty years. His current
research interest, i.e. what he would like to do if he had time is in the area
of parallel programming, transactional memory, C++ benchmark performance, object
model, generic programming and template metaprogramming. He holds a B.Sc from
University of Toronto, and a Masters in Mathematics from University of Waterloo.
He has been asked to speak at ACCU, C++Now, Meeting C++, ADC++, CASCON,
Bloomberg, CERN, and many Universities, research centers and companies.
John Glossner, President of the Heterogeneous System Architecture
Foundation (HSAF), CEO of Optimum Semiconductor Technologies
Heterogeneous Systems Era
Heterogeneous processing represents the future of computing, promising to unlock
the performance and power efficiency of parallel computing engines found in most
modern electronic devices. This talk will detail the HSA Foundation (HSAF)
computing platform infrastructure including features/advantages across computing
platforms from mobile and tablets to desktops to HPC and servers. The talk will
focus on technical issues solved by HSAF technologies. The presentation will
also discuss important new developments that are bringing the industry closer to
broad adoption of heterogeneous computing.
Dr. John Glossner is President of the Heterogeneous System Architecture
Foundation (HSAF) and CEO of Optimum Semiconductor Technologies. OST and its
processor division General Processor Technologies (GPT-US). Previously he
served as Chair of the Board of the Wireless Innovation Forum. In 2010 he joined
Wuxi DSP (a licensee of Sandbridge technology and parent company of OST) and was
named a China 1000 Talents. He previously co-founded Sandbridge Technologies and
received a World Economic Forum award. Prior to Sandbridge, John managed both
technical and business activities in IBM and Lucent/Starcore. John received a
Ph.D. in Electrical Engineering from TU Delft in the Netherlands, M.S degrees in
E.E. and Eng. Mgt from NTU, and a B.S.E.E. degree from Penn State. He has more
than 40 patents and 120 publications.